13 Oct 2014

IEEE VLSI Projects Title 2014-2015




VLSI - FPGA Projects 2014 - 2015







S.No
Title
Domain
1

A low-hardware consumption FPGA based configurable LDPC decoder

VLSI
2

A Novel VLSI DHT Algorithm for a Highly Modular and Parallel Architecture

VLSI
3

A Novel Approach for Parallel CRC generation for high speed application Design of High Performance 64 bit MAC Unit

VLSI
4

RADIX 10 PARALLEL Decimal Multiplier

VLSI
5

A higher radix FFT FPGA implementation suitable for OFDM systems

VLSI
6

A Distributed Canny Edge Detector: Algorithm and FPGA Implementation

VLSI
7

Performance analysis of FPGA based Sobel edge detection operator

VLSI
8

Vehicle image edge detection algorithm hardware implementation on FPGA

VLSI
9

An FPGA Implementation of Gradient Based Edge Detection Algorithm Design

VLSI
10

Hardware implementation of truncated multiplier based on multiplexer using FPGA

VLSI
10

FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter

VLSI
10

CSD(Canonical signed digit) multipliers for FPGA DSP applications

VLSI
10

Enhanced Memory reliability against multiple cell upset using decimal matrix code

VLSI
10

A Simple Pipelined Logarithmic Multiplier

VLSI
10

Design and implementation Reversible BCD adder

VLSI
10

High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics

VLSI
10

A High-speed 32-bit Signed/Unsigned Pipelined Multiplier

VLSI
10

FPGA based data acquisition and analysis system

VLSI
10

Design and implementation of truncated multipliers for precision improvement

VLSI
10

Design of High Performance 64 bit MAC Unit

VLSI
10

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

VLSI
10

Performance evaluation of FPGA based crossbar NoC architecture

VLSI
10

Design of AES (Advanced Encryption Standard) Encryption and Decryption IP core

VLSI
10

FPGA Implementation of IRDA IP core

VLSI
10

Design of JPEG Image compression standard

VLSI
10

FPGA Implementation of Triple DES

VLSI
10

Pipelined Parallel FFT Architectures via Folding Transformation

VLSI
10

Implementation of Radix2 ACS in Adaptive Viterbi decoder

VLSI
10

Analysis, Verification And FPGA Implementation Of Vedic Multiplier

VLSI









No comments:

Post a Comment

Note: only a member of this blog may post a comment.